Material and device structure on silicon

Phase 1: Material and device structure on silicon
The channel region between the source and drain must be formed on top of a grid structure of silicon called a lattice. The lattice spacing of III-V materials differs from that of silicon. When the atoms in the structure of each material get far apart, they can't connect due to lattice mismatch.

To avoid this, Intel and our partners have jointly developed graded, thin, non-silicon buffer layers that avoid defects while keeping the III-V channel intact. These buffer layers include gallium arsenide (GaAs) and indium aluminium arsenide (InAlAs), creating a III-V semiconductor composite metamorphic buffer structure on top of the silicon substrate. The metamorphic buffer filters out dislocations caused by the material mismatches, leaving a high-quality channel region.

To facilitate the integration with silicon CMOS, Intel has reduced the buffer thickness as much as possible, without impacting the overall material quality.

Phase 2: Device integration and processing.

The transistors must be fabricated based on the buffer layers, so the next step is to develop the process for creating devices on the wafer. Our methods evolve with each experiment—for example, the contact resistance might be too great, and one way to reduce it might be to use different contact metals. In order to improve the contact resistance we might change the III-V source/ drain material by increasing indium concentration.

Phase 3: Device measurement and analysis
In the last step, all experimental transistors must be tested. For each, there is characterization, analysis, and theory. These results are charted against a baseline of theory, or expectations, to see where a particular device deviates. We can then determine the advantages of the new technology in relation to the old technology. To do so, we develop unique test structures to measure the effective velocity of electrons traveling through the transistor channel (mobility).
With nanometer-scale measurements, we can determine whether the better electron mobility in these new materials will result in some real transistor gain over current technologies.

Research progress being made
The research community is looking for ways to make III-V materials work because of the potential performance and power benefits, as well as the ability to integrate communications and optoelectronic circuits with CMOS logic on the same silicon chip. In the future, III-V devices and silicon CMOS transistors may coexist on the same silicon chip for increased performance and functionality with enhanced energy efficiency.

Although there are many difficult challenges to overcome, significant progress has been made by the research community. Always looking toward the future, Intel and our partners have recently demonstrated the world's first high-speed P-channel devices and expect to disclose their results at IEDM in December 2008.
"Although there are many difficult challenges to overcome, significant progress has been made by the research community and much excitement has been generated. Going forward, research on III-V-based transistors and their integration on large silicon wafers will be even more exciting and rewarding than ever," states Robert Chau, Intel senior fellow and director of transistor research and nanotechnology.